1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device where a plurality of semiconductor chips are mounted on a substrate.
2. Background Art
As a package of high-speed DRAMs or the like, a package using a BOC (board on chip) structure has been known. FIG. 15 is a schematic sectional view showing a package using a BOC structure. In a package having a BOC structure, a substrate 101 having an opening 101a in the center portion thereof is used. A semiconductor chip 102 is die-bonded upside down on the substrate 101, and disposed so that the location of the center pad 102a corresponds to the location of the opening 101a of the substrate 101. The semiconductor chip 102 is electrically connected to the substrate 101 with a gold wire 103, and the gold wire 103 is passed through the opening 101a, and wire-bonded to the center pad 102a and the bonding finger 101b on the back of the substrate 101.
FIG. 16 is a plan showing the surroundings of the opening 101a viewed from the bottom before the package of FIG. 15 is resin-sealed. Gold wires 103 drawn from center pads 102a are connected to the bonding fingers 101b of the substrate 101, and the bonding fingers 101b are connected to the patterns or the like whereon ball bumps 104 shown in FIG. 15 are disposed. As FIG. 15 shows, the back of the semiconductor chip 102 and the surroundings of the opening 101a are sealed with the sealing resin 105.
FIG. 17 is a schematic sectional view showing a substrate-type package. In a substrate-type package, a semiconductor chip 102 is die-bonded on the substrate 101 with the center pad 102a thereof facing up. A gold wire 103 connected to the center pad 102a is drawn on the surface of the semiconductor chip 102, and connected to a bonding finger on the substrate 101 positioned outside the semiconductor chip 102.
FIG. 18 is a schematic sectional view showing a multi-chip package using a BOC structure. This multi-chip package has a constitution wherein the semiconductor chip 102 of FIG. 17 is die-bonded on the semiconductor chip 102 of FIG. 15, and the two semiconductor chips 102 provided with a center pad 102a are die-bonded with one upside down. As FIG. 18 shows, the center pad 102a of the upper semiconductor chip 102 is connected to the upper surface of the substrate 101 with a gold wire 103. The gold wire 103 connected to the center pad 102a of the lower semiconductor chip 102 is connected to the lower surface of the substrate 101 through the opening 101a. 
However, in the multi-chip structure shown in FIG. 18, stacking two semiconductor chips 102 raises the position of the center pad 102a of the upper semiconductor chip 102, and in order to connect the center pad 102a to the substrate 101, the gold wire 103 must be sufficiently long. Since the gold wire 103 is supported only by wire-bonded portions on the both ends, the fall (gold wire flowing) is likely to occur in the middle between wire-bonded portions when the total length of the gold wire 103 becomes long. Thereby, a problem of short-circuiting between gold wires 103 adjacent to each other, or between a gold wire 103 and the edge of the semiconductor chip 102 has risen.
In addition, since the wiring drawing length of the gold wire 103 to be connected to the lower semiconductor chip 102 is longer than the length of the gold wire 103 to be connected to the upper semiconductor chip 102, timing difference in signals between upper semiconductor chip 102 and lower semiconductor chip 102 is significant especially during high-speed operations. Thereby, a problem of low reliability of the device operation has risen.